The present invention relates to a data processing system, i.e., a hardware unit for logical manipulation (linkage) of data (information) available in binary form.
Data processing systems of this type have by now been known long since, and they have already found broad application and recognition. The basic structure and operation of prior data processing systems can be defined approximately as comprising an arithmetic-logic linking unit in which the data to be linked are processed according to program instructions (software). In the process, the data are retrieved appropriately via a controller by more or less complex addressing procedures and, to begin with, kept ready in working registers. Following the logical linkage, the new data are then filed again in a preset memory location. The arithmetic-logic linkage unit consists of logical linking modules (gates, members) that are coupled to one another in such a way that the data to be manipulated allows in accordance with the underlying software logical processing using the four basic arithmetic operations.
It is easily perceivable that on the basis of the known structures there is relatively much computing time required for reading the data to be manipulated, transferring the data to the working registers, passing the data on to specific logic modules in the arithmetic-logic linking unit and, lastly, store the data again. Also, it is readily evident that the hardware structure of the arithmetic-logic linking unit cannot be considered as optimal inasmuch as the integrated logic hardware modules are actively used within the overall system always only in one and the same way. Similarly, a compilation of functions in so-called pipelines is very much impeded or restricted by strict hardware specification, which of necessity means frequent register reloading between working registers and central processing unit. Furthermore, such modules lend themselves poorly to cascading and require then substantial programming work.
An additional advantage of the present invention is that a widely scalable parallelity is available. Created here is a basis for a fast and flexible creation of neuronal structures such as to date can be simulated only at considerable expense.
The objective underlying the present invention is to propose a data processing system which hereafter will be referred to as data flow processor (DFP), where a greater, or better, flexibility of the overall structure and data flow as well as pipelining and cascading options result in increased processor capacity, or linking capacity.
Besides its employment as strictly a data flow processor, the DFP is meant to be able to handle the following further tasks:
utilization as universal module in setting up conventional computers, making the structure simpler and less expensive; PA1 utilization in neuronal networks.
This objective is accomplished by providing an integrated circuit (chip) with a plurality of cells which, in particular, are arranged orthogonally to one another, each with a plurality of logically same and structurally identically arranged cells, whose arrangement and internal bus structure is extremely homogeneous so as to facilitate programming. Nonetheless, it is conceivable to accommodate within a data flow processor cells with different cell logics and cell structures in order to increase the capacity in that, for example, there exist for memory access other cells than for arithmetic operations. A certain specialization can be advantageous, especially for neuronal networks. Coordinated with the cells is a loading logic by way of which the cells, by themselves and facultatively grouped in so-called MACROs, are so programmed that, for one, selective logical functions but, for another, also the linking of cells among themselves can be realized widely. This is achieved in that for each individual cell a certain memory location is available in which the configuration data are filed. These data are used to switch multiplexers or transistors in the cell so as to guarantee the respective cell function (refer to FIG. 12).